In commonly assigned U.S. Pat. Nos. 5,291,269 (3/1/94), 5,293,214 (3/8/94) and 5,333,049 (7/26/94) the inventor discloses methods and apparatus for determining a thickness of a layer of material. For example, in the '049 patent the inventor discloses a full aperture measurement instrument for determining a thickness of a layer disposed on a substrate. The substrate may be a semiconductor wafer. A light source is used for illuminating a surface of the layer, and a CCD camera is employed for obtaining an image of the illuminated surface. The image obtained from the camera is converted into a map of measured reflectance data, which is subsequently compared to reference reflectance data. The result is the generation of a map describing a thickness profile of the layer.
Although the techniques described in these commonly assigned U.S. Patents are very well suited for their intended applications, a problem is created when the underlying surface of the wafer is patterned, as is typically the case when a semiconductor wafer is being processed to form integrated circuits. In this case the illumination that passes through the surface layer, which may be a layer of SiO.sub.2 used as a Chemical-Mechanical Polishing (CMP) layer, is scattered and diffracted by the underlying circuit features. These features often take the form of short, repetitive linear structures which, due to their small size and close spacings, can function as wavelength selective diffraction gratings. The scattering and diffraction of the illumination results in a significant reduction in the amount of illumination that reaches the camera, often by as much as 30% to 50%, over the case where the underlying substrate or wafer is smooth and not patterned. Furthermore, the optical system for a full aperture thickness measurement system is typically incapable of resolving the micron and sub-micron sized circuit features. In addition, the patterning of the wafer surface varies widely over the surface, depending on what type of integrated circuit structures are being fabricated within a given area. As a result, it is very difficult to accurately model the optical behavior of the wafer/layer system, thus severely complicating the task of generating accurate reference reflectance data for use in comparing to an obtained image.
Presently available equipment that is used to measure film thicknesses on patterned wafers uses microscope objectives which view only one small region on the wafer. The presently available equipment has many other disadvantages. One disadvantage results from the use of a microscope which provides high magnification, but at the expense of a small f-number and correspondingly large light collection angle. The large light collection angle allows diffracted and scattered radiation to enter the optical system and to interfere with the specular reflection from the film layers being measured. It is extremely difficult or impossible to separate these two contributions, since they both are detected by the same optical detector.
A second disadvantage results from a requirement to locate the microscope objective at a precise point in the field so as to avoid diffracting areas. This requires the use of an accurate x-y wafer positioning stage, and further requires precise knowledge of the details of the spatial arrangement of the circuit features.
In addition, currently available systems do not utilize the benefits that accrue from image collection or image processing in order to enhance the measurement of thin layers or films.
The aforementioned CMP layer is typically applied so as to planarize the surface of the wafer as it is processed. As circuit features are incrementally formed during wafer processing the height of the surface of the wafer tends to vary widely. This variation in height over the wafer surface complicates the subsequent accurate placement of further circuit structures. Also, focussing becomes more difficult resulting in lower chip yields. To overcome these problems it is known to deposit a dielectric layer, such as a CV deposited layer of SiO.sub.2, and to then chemically and mechanically polish the dielectric layer (i.e., the CMP layer), thus providing a smooth and uniform electrically insulating layer upon which to continue to form further circuit structures. In this case apertures are made through the CMP layer as required to contact already formed circuit features. In order to accurately planarize the CMP layer it is thus required to accurately know the thickness of the CMP layer, at a plurality of locations, so as not to remove too much of the CMP layer. If this were to occur the destruction of the underlying circuits could result. Even if the underlying circuits are not damaged; if the CMP layer is made too thin the dielectric characteristics of the CMP layer may be impaired, resulting in short circuits developing between circuit features located above and below the CMP layer.
It can be appreciated that a semiconductor wafer in an intermediate stage of processing can represent a very significant investment in both processing time and money. It can therefore further be appreciated that it is an important requirement to accurately determine the thickness profile of the CMP layer. It is also important to accurately determine the thickness profile of other types of intermediate layers that may be deposited on existing patterns for, by example, quality control and diagnosis purposes.
It is thus one object of this invention to accomplish the determination of the thickness profile of one or more layers or films in a rapid manner so as not to unduly impact the throughput of a semiconductor fabrication line. It is a further object of this invention to accomplish the determination of the thickness profile of one or more layers or films without requiring a priori knowledge of the types of underlying scattering and diffracting features, their geometry, or their locations (both spatial and/or angular), and to also not require the use of precise positioning tables and the like.